1. Field of the Invention
The invention relates to a circuit arrangement for rectifying an AC voltage signal generated by a signal source where the circuit has a differential amplifier including at least a first and a second transistor and where the a.c. voltage signal is supplied to inputs of both transistors.
2. Background of the Invention
A circuit arrangement of this kind is known from "Halbleiterschaltungstechnik" ("Semiconductor circuitry") by U. Tietze and Ch. Schenk, Springer-Verlag 1978, 4th edition, FIG. 25.13. In this, the AC voltage signal is fed to a transistor in the differential amplifier stage while the base electrode of the second transistor is at a reference potential. The collector potentials of these two differential amplifier transistors are fed to two emitter followers connected in parallel so that the positive collector potential is transferred in each case to the output.
Another circuit for the rectification of AC voltage signals is known from "Analog IC design: the current-mode approach" by C. Tamazou, F. J. Lidgey and D. G. Haigh, published by Peter Peregrinus Ltd, London 1990, FIG. 2.10, in which the rectified signal has an approximately quadratic characteristic. This circuit is shown in FIG. 5 and includes three npn transistors T7, T8 and T9. The emitter surface area of the middle transistor T8 is n times greater than the equivalent surface areas of the other two transistors T7 and T8. The emitter electrodes of these three transistors are fed from a single constant current source that supplies a current I1. A resistor R7 is connected between the bases of transistors T7 and T8 and another resistor R8 with identical resistance value is connected between the bases of transistors T8 and T9. Consequently, an a.c. voltage signal Ue supplied from a signal source 4 is fed directly to the base electrode of transistor T7, but only one-half of this signal is fed to transistor T8. Finally, the collector electrodes of transistors T7 and T9 are connected directly to an operating voltage source UB whereas that of the middle transistor T8 is connected to this operating voltage source via a load resistance R9. The function of this circuit will now be explained below with reference to the Ue - Ic diagram as shown in FIG. 6. With a surface area ratio n between the transistors T8 and T7 and also between T8 and T9, in the quiescent state a collector current Ic8 of transistor T8 flows with a magnitude of I1.multidot.n/(n+2) through the load resistor R9. In the diagram shown in FIG. 6, this is the intersection of the curve Ic8 with the ordinate axis.
With an input voltage Ue.noteq.0, however, the transistor T7 or T9 takes an increasingly large proportion of the current as curves Ic7 and Ic8 in FIG. 6 show. At the same time, current Ic8 reduces and its curve in the region of zero of the input voltage Ue (see region d in FIG. 6) approximates a parabola of the second degree. Consequently the voltage at the collector of transistor T8 rises above the quiescent state value. This corresponds to a rectification of the a.c. voltage signal Ue with quadratic characteristic.
In this known circuit in accordance with FIG. 5, however, the power consumption in the two resistors R7 and R8 is disadvantageous. Moreover, for this circuit to operate reliably, a high input voltage Ue is required.